Some high performance circuits such as, for example, microprocessors, are implemented using dynamic logic gates. As is well known, dynamic logic gates in general allow the design of faster circuits compared to conventional CMOS circuits. Generally, dynamic logic gates operate in a precharge phase and an evaluation phase. For example, FIG. 1 schematically illustrates a typical conventional dynamic logic gate 100 of the domino type. In this example, the logic gate 100 implements a three-input AND gate. The logic gate 100 includes a precharge p-channel transistor PC and an evaluation n-channel transistor EV, each having a gate coupled to receive a clock signal CK. The logic gate 100 also includes three n-channel transistors N1-N3 connected in series (i.e. with channel regions connected end-to-end) between the drains of the precharge and evaluation transistors PC and EV. The gates of these three n-channel transistors are connected to respectively receive three input signals A, B, and C. The drain of the precharge transistor PC is also connected to a CMOS inverter 102 (implemented by a p-channel transistor P1 and an n-channel transistor N4) through a node OUTN. The CMOS inverter 102 provides an output signal OUT at an output lead 104.
FIG. 2 is a timing diagram illustrating the operation of the logic gate 100. Although the operation of the logic gate 100 is well known to those skilled in the art of dynamic logic gates, the following description is provided for completeness. A falling edge of the clock signal CK initiates a precharge phase by turning on the precharge p-channel transistor PC and turning off the evaluation n-channel transistor EV. Consequently, during the precharge phase, the precharge transistor PC pulls up the voltage at the node OUTN, thereby causing the CMOS inverter 102 to generate the output signal OUT with a logic low level.
In contrast, a rising edge of the clock signal CK causes the logic gate 100 to enter the evaluation phase by turning off the precharge transistor PC and turning on the evaluation transistor EV. As a result, during the evaluation phase, the precharge transistor PC no longer pulls up the voltage at the node OUTN. In addition, the series connected n-channel transistors N1-N3 and the evaluation transistor EV can implement a conductive path between the node OUTN and ground (e.g., the VSS voltage source). In this example, the input signals A, B, and C all transition to a logic high level during the evaluation phase, thereby causing the n-channel transistors N1-N3 to turn on and discharge the node OUTN. Accordingly, the inverter 102 causes the output signal OUT to transition to a logic high level. Of course, had one or more of the input signals A-C remained at a logic low level during this evaluation phase, the pulldown path would have remained open-circuited, causing the node OUTN and the output signal OUT to remain at a logic high and logic low level, respectively.
FIG. 3 illustrates an exemplary logic subcircuit 300 implemented with interconnected dynamic logic gates 301-306. A flip-flop circuit 308 is connected to provide one or more input signals to the dynamic logic gates 301-306. A flip-flop circuit 310 is connected to receive one or more output signals generated by the dynamic logic gates 301-306. It will be understood by those skilled in the art of dynamic logic that large numbers of subcircuits similar to the logic subcircuit 300 can be interconnected to form a complex circuit such as a microprocessor. A single clock signal CK is used to clock all of the logic gates and flip-flop circuits of the logic subcircuit 300. As a result, while the clock signal CK is at a logic low level (i.e., during the precharge phase) the logic subcircuit 300 performs no logic function. Because the precharge phase of a typical dynamic flip-flop requires about 20%-30% of the cycle time in current CMOS processes, only about 70%-80% of each clock cycle is available for logic operation. The "wasted" 20%-30% results in sub-optimal operation of the logic circuit 300 from a logic operation perspective.
One conventional scheme to more efficiently use each clock cycle is illustrated in FIG. 4. In this scheme, a logic subcircuit 400 is configured so that the flip-flop circuit 308 and the dynamic logic gates 301-303 are connected to receive a first clock signal CK1. The logic gate 303 is connected to provide one or more output signals to a rising edge triggered latch 401, which in turn provides one or more output signals to the dynamic logic gates 304-306. The latch 401 and the logic gates 304-306 are clocked with a second clock signal CK2.
In this type of scheme, the clock signals CK1 and CK2 implement a "non-overlapping" two-phase clocking system. More specifically, as shown in FIG. 5, the clock signal CK2 is the complement of the clock signal CK1. Thus, the precharge and evaluation phases of the clock signal CK1, respectively, do not overlap the precharge and evaluation of the clock signal CK2. Because the clock signals do not overlap, the logic gates driven by the latch 401 will be operating in the precharge phase when the logic gates driven by the flip-flop circuit 308 are operating in the evaluation phase and vice versa. Thus, for example, when the clock signal CK1 is at a logic high level, the logic gates 301-303 perform a logic function on the input signals provided by the flip-flop circuit 308. During this time period, the latch 401 receives the clock signal CK2 with a logic low level, which causes the latch 401 to be disabled. Then, when the clock signals CK1 and CK2, respectively, transition to the logic low and logic high levels, the output signal(s) of the logic gates 301-303 are latched by the latch 401 and provided to the logic gates 304-306, which are now in the evaluation phase. Unlike the logic subcircuit 300 (FIG. 3), this scheme allows the logic subcircuit 400 to perform logic operations during the entire cycle time by "hiding" the precharge time of one group of logic gates during the evaluation phase of the other group of logic gates.
However, the non-overlapping two-phase clocking system has several shortcomings. For example, the latch 401 undesirably increases the propagation delay of the subcircuit by about one gate delay. In addition, skew and jitter between the clock signals CK1 and CK2 is generally accounted for by increasing the set-up time of the latch, resulting in a wasted use of a portion of the cycle time. That is, the latency of the latch 401, in effect, takes time out of the cycle time, thereby reducing the time available in the cycle time for performing logic operations.
Still further, as is well known in the art of dynamic logic, the latch 401 in conjunction with the complementary two phase clocking causes the so-called "quantization effect" which results when the "first" group of logic gates (i.e., logic gates 301-303 in this example) does not have substantially the same propagation delay as the "second" group of logic gates (i.e., logic gates 304-306 in this example). Perfect balance is hard to achieve in practice because of the quantized nature of gate delays. This quantization effect may add up to a gate delay penalty. The combined time penalties due to the insertion of the latch 401 are between approximately two and three gate delays. Thus, there is a need for a method of generating clock phases for the dynamic logic subcircuit that efficiently uses the entire cycle time for logic operations without the time penalties of the non-overlapped two-phase clocking system.